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    • 专利摘要:
    PURPOSE: An apparatus for calculating an average picture level of an image is provided to reduce the number of gates by using a serial dividing method to calculate the average picture level. CONSTITUTION: An apparatus for calculating an average picture level of an image includes an accumulator portion(301), a comparator(302), and a counter(303). The accumulator portion(301) adds image data to feedback data and stores a reduced value as much as the number of frame to pixel according to an adding result when a horizontal synchronous signal and a vertical synchronous signal are in an active state. The comparator(302) is used for comparing the adding result to the number of frame to pixel and storing the compared result. The counter(303) is used for outputting an average picture level of an image only if the adding result is larger than the number of frame to pixel.
    公开号:KR20030080161A
    申请号:KR1020020018675
    申请日:2002-04-04
    公开日:2003-10-11
    发明作者:김상연
    申请人:엘지전자 주식회사；
    IPC主号:
    专利说明:

    Apparatus for calculating APL}
    [13] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an average picture level calculation device which is used as a reference for determining the number of emission of light in a plasma display panel (PDP).
    [14] Recently, research and development on various display devices have been progressed, and a plasma display device (PDP) has been attracting attention as a large-screen flat display device capable of displaying characters and images clearly.
    [15] The plasma display device (PDP) is a device that expresses the gray scale through the number of light emission of the display cell. Here, the number of emission of light has a relationship with power consumption in FIG. 1A.
    [16] As shown in FIG. 1A, the power consumption increases as the number of light emission increases, so to limit the power consumption to a predetermined value, the number of light emission must be adjusted. In this case, an average picture level (APL) of an image is used as a reference signal.
    [17] FIG. 1B shows the number of light emission controlled according to the APL value, and FIG. 1C shows power consumption limited by the number of light emission control.
    [18] The APL is also used for white balance adjustment as well. That is, since the luminance ratio of each phosphor is not constant according to the number of light emission times in the PDP, the change in light emission time affects the white balance. Therefore, the white balance is adjusted based on the APL value in order to maintain the white balance even with the change in the number of emission.
    [19] 2 is a block diagram of a general APL calculation apparatus.
    [20] 2, the input image data is accumulated in the first accumulator 201 while the horizontal sync signal is active, and the horizontal sync signal is inactive while the vertical sync signal is active. The data of the first accumulator 201 is accumulated by the second accumulator 202 at the time of the change to -active, and all the pixels in one frame of the image are added.
    [21] That is, the adder 201a of the first accumulator 201 adds input image data and data fed back from the register 201b and outputs the result to the register 201b. The register 201b stores the output data of the adder 201a while the horizontal sync signal is active, and then outputs the stored data to the second accumulator 202 at the time when the horizontal sync signal is inactive. do.
    [22] The adder 202a of the second accumulator 202 adds output image data of the first accumulator 201 and data fed back from the register 202b and outputs the result to the register 202b. The register 202b stores the output data of the adder 202a while the vertical sync signal is active, and then resets the stored data to the divider 204 at the time when the vertical sync signal is inactive. At this time, the rising trigger pulse generator 203 detects the rising time of the horizontal synchronization signal, that is, the inactive time, generates a pulse corresponding thereto, and outputs the corresponding pulse to the register 202b of the second accumulator 202. The register 202b stores the data of the adder 202b at the time when the horizontal sync signal becomes non-active.
    [23] The divider 204 divides the addition result of all pixels in one frame output from the second accumulator 202 by the pixel number of per frame and outputs the result. In other words, the divider 204 results in an APL value.
    [24] The problem with this structure is that since the number of bits of data required for each operation is large, the implementation requires a large number of gates. For example, if image data is quantized to 8 bits and the display format is 1280x720p, the register 201b of the first accumulator 201 needs to accumulate 8-bit data 1280 times. Since the register 202b of the second accumulator 202 must accumulate the 19-bit horizontal accumulated value 720 times vertically, it is implemented as a 29 (19 + 10) bit register.
    [25] In addition, the two adders 201a and 202a in FIG. 2 are implemented with 8-bit and 19-bit, 19-bit and 29-bit adders, respectively. In particular, the divider 204 requires a very large divider with 29 bits dividing and 21 bits dividing.
    [26] SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to use an APL of an image used as a reference signal for emission count and white balance adjustment using a serial dividing method consisting of a counter and a comparator. By calculating, it is to provide an image APL calculation device for simplifying the hardware.
    [1] Figure 1a is a graph showing the relationship between the number of light emission and power consumption in a typical PDP
    [2] Figure 1b is a graph showing the relationship between the APL and the number of emission in a typical PDP
    [3] 1c is a graph showing the relationship between APL and power consumption in a typical PDP
    [4] 2 is a block diagram of a conventional APL calculation apparatus
    [5] 3 is a block diagram of an APL calculation device according to the present invention;
    [6] 4A to 4E are operation timing diagrams of the parts of the APL calculating device of FIG.
    [7] Figure 5 is a block diagram showing another embodiment of the APL calculation apparatus according to the present invention
    [8] Explanation of symbols for main parts of the drawings
    [9] 301,401 Accumulator 301a, 401a Adder
    [10] 301b, 401c: Register 302,402: Comparator
    [11] 303,403 Subtractor 304,401b Multiplexer
    [12] 305,404 Counter 306,405 End gate
    [27] In order to achieve the above object, the APL calculation apparatus for an image according to the present invention adds the input image data and the feedback data while both horizontal and vertical synchronization signals are active, and then adds more than the number of pixels per frame. An accumulator for storing the addition result or a value reduced by the number of pixels per frame in the addition result, a comparator for comparing the addition result of the accumulator and the number of pixels per frame and outputting the result to the accumulator; And a counter that is enabled while both the horizontal and vertical synchronization signals are active, and increments only when it is determined by the comparator that the addition result of the accumulator is greater than the number of pixels per frame, and outputs an average luminance level value of the image. And multiplying a vertical synchronizing signal by an output signal as an enable signal to a register and a counter of the accumulator part; It is characterized in that comprises section.
    [28] The accumulator includes an adder for adding input image data and feedback data, a register enabled by an output of the calculator, a register for storing the addition result of the adder, and a subtractor for subtracting the number of pixels per frame from the value output from the register. And a selector which selects an output of the subtractor when the output value of the adder is greater than the number of pixels per frame in the comparator, and selects an output of the register and feeds back to the adder when it is determined that the output value of the adder is not large. It is characterized by.
    [29] The accumulator selects an adder that adds input image data and feedback data, and selects a value obtained by subtracting the number of pixels per frame from the output of the adder when the comparator determines that an output value of the adder is larger than the number of pixels per frame. If not determined, the selector for selecting and outputting the output of the adder, enabled by the output of the calculator, a register for storing the value output through the selector and feeding back the stored value to the adder, the adder And a subtractor outputting the selector by subtracting the number of pixels per frame from the output value of.
    [30] Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings.
    [31] Hereinafter, with reference to the accompanying drawings illustrating the configuration and operation of the embodiment of the present invention, the configuration and operation of the present invention shown in the drawings and described by it will be described as at least one embodiment, By the technical spirit of the present invention described above and its core configuration and operation is not limited.
    [32] FIG. 3 is a block diagram illustrating an APL calculation device according to the present invention, wherein an accumulator for adding and storing image data input and feedback data C while horizontal and vertical sync signals are active. 301, a comparator 302 for comparing the addition result A of the accumulation unit 301 and the number of pixels B per frame, and an addition result A of the accumulation unit 301 in the comparator 302. Is increased only when it is determined to be larger than the number of pixels B per frame B, and outputs an APL value, and enables the accumulator 301 and the counter 303 by ANDing the horizontal and vertical synchronization signals. And an end gate 304 for outputting a signal.
    [33] The accumulator 301 is enabled by an output of the AND gate 304 and synchronized with an adder 301a and a clock CLK, which adds input image data and feedback data C. The adder 301a is added to the adder 301a. The register 301b for storing the result A, the subtractor 301c for subtracting the number of pixels B from the value D stored in the register 301c, and the comparator 302, The multiplexer 301d selects an output value D of the register 301b or an output value DB of the subtractor 301c and feeds it back to the adder 301a.
    [34] 4A to 4E are operation timing diagrams of the respective parts of the APL calculation apparatus of FIG. 3, wherein (a) is a clock, (b) is input image data, and (c) is stored in a register 301b. Data (d) shows the comparison result of the comparator 302 and (e) shows the count result of the counter 303.
    [35] In the present invention configured as described above, the adder 301a of the accumulator 301 adds the input image data and the feedback data C output from the multiplexer 301d and outputs them to the register 301b and the comparator 302. The AND gate 304 logically multiplies the horizontal synchronizing signal with the vertical synchronizing signal and outputs the enable signal to the register 301b and the counter 303 of the accumulator 301. That is, the enable signal is output only when both the horizontal synchronizing signal and the vertical synchronizing signal are active. The register 301b is enabled by a signal output from the AND gate 304 to store the addition result A of the adder 301a. The value D stored in the register 301b is output to the subtractor 301c and the multiplexer 301d in synchronization with the clock CLK. The subtractor 301c subtracts the number of pixels B per frame from the output data D of the register 301b and outputs the result D-B to the multiplexer 301d.
    [36] The comparator 302 compares whether the addition result A of the adder 301a of the accumulator 301 is larger or smaller than the number of pixels B per frame, and compares the result of the comparison with the counter 303 and the multiplexer 301d. Output with the selection signal of).
    [37] At this time, when the comparator 302 determines that the addition value A of the input data and the feedback data C is larger than the number of pixels B per frame (A> B), the counter 303 is incremented. The value C fed back to the adder 301a through the multiplexer 301d is a value DB obtained by reducing the value D stored in the register 301b by the number of pixels B per frame.
    [38] In the case where the comparator 302 determines that the addition value A of the input data and the feedback data C is not greater than the number of pixels B per frame (A ≤ B), the counter 303 currently The value C that is maintained and is fed back to the adder 301a through the multiplexer 301d becomes the value D that is output from the register 301b.
    [39] That is, the multiplexer 301d uses the signal output from the comparator 302 as a selection signal to output data D of the register 301b of the accumulator 301 or output data DB of the subtractor 301c. ) Is fed back to the adder 301a of the accumulator 301.
    [40] This is represented by Equation 1 below.
    [41]
    [42] At this time, the register 301b is reset at the time when the vertical synchronization signal is inactive, and the counter 303 resets while outputting a value counted at the time when the vertical synchronization signal is inactive.
    [43] Therefore, the value output from the counter 303 becomes an APL value.
    [44] In FIG. 4, it can be seen that when the output of the comparator 302 is high, the accumulated value stored in the register 301b decreases by the number of pixels per frame with the increase of the counter 303.
    [45] For example, suppose that the number of pixels per frame is 16, and input image data is input in order from 1 to 16 as shown in FIG. 4.
    [46] On the other hand, when the input video data is 5, since 10 is stored in the register 301b, the output of the adder 301a is 15. That is, the output A of the adder 301a is smaller than the number of pixels B per frame (A <B). Therefore, the comparator 302 outputs a low signal, the counter 303 maintains the current value, and the multiplexer 301d selects the output data D of the register 301b and outputs it to the adder 301a. do. The adder 301a adds 5, which is input image data, and 10, which is feedback data, and stores the result in the register 301b. That is, 15 is stored in the register 301b.
    [47] Then, when the image data 6 is input as shown in Fig. 4B, 15 is stored in the register 301b as shown in Fig. 4C, so that the output of the adder 301a is 21 at this time. Thus, the comparator 302 determines that the output of the adder 301a (i.e., A = 21) is greater than the number of pixels per frame (i.e., B = 16) and as a result, the high signal is sent to the counter 303 and the multiplexer. Output to 301d. When the high signal is output from the comparator 302, the counter 303 increases by 1 as shown in FIG. 4E, and the multiplexer 301d outputs the subtractor 301c (that is, DB = 15-16 = −). 1) is output to the adder 301a. The adder 301a adds 6, which is input image data, and -1, which is data C fed back through the multiplexer 301d, and stores the result, 5, in the register 301b as shown in FIG. do.
    [48] When this process proceeds to 16 pixels, the final output of the counter 303 becomes 8 as shown in FIG. 4E, and this value becomes an APL value.
    [49] 5 is another embodiment of a detailed circuit of the APL calculation apparatus according to the present invention, and the result is shown in FIG. 3. That is, when the output of the comparator 402 is high, the accumulated value stored in the register 401c decreases by the number of pixels per frame with the increase of the counter 403.
    [50] Referring to FIG. 5, the accumulator 401 outputs an adder 401a that adds image data and data D fed back from the register 401C, and an output A of the adder 401a according to the output of the comparator 402. Alternatively, the multiplexer 401b which selects and outputs the value AB obtained by subtracting the number of pixels B per frame from the output A of the adder 401a and the output of the AND gate 404 to enable the multiplexer 401b. Register 401c for storing the data outputted from the &lt; RTI ID = 0.0 &gt;), and a subtractor 401d for outputting, to the multiplexer 401b, a value AB obtained by subtracting the number B of pixels B from the output A of the adder 401a. It is composed of The output D of the register 401c is fed back to the adder 401a, and the output of the comparator 402 is used as a selection signal of the multiplexer 401b. At this time, the register 401c is reset at the time when the vertical synchronization signal is inactive, and the counter 403 is reset at the same time as outputting the value counted at the time when the vertical synchronization signal is inactive.
    [51] For example, suppose that the number of pixels per frame is 16, and the input image data is input in order from 1 to 16. On the other hand, when the input image data is 5, since 10 is stored in the register 401c, the output of the adder 401a is 15. That is, the output A of the adder 401a is smaller than the number of pixels B per frame (A <B). Accordingly, the comparator 402 outputs a low signal, the counter 403 maintains the current value, and the multiplexer 401b selects the output data A of the adder 401a and stores it in the register 401c. do. That is, 15 is stored in the register 401c.
    [52] Then, when the video data 6 is input, 15 is stored in the register 401c, so that the output of the adder 401a at this time is 21. Accordingly, the comparator 402 determines that the output of the adder 401a (i.e., A = 21) is greater than the number of pixels per frame (i.e., B = 16), and as a result, the high signal is sent to the counter 403 and the multiplexer. Output to 401b. The counter 403 increases by one when the high signal is output from the comparator 402, and the multiplexer 401b selects the output of the subtractor 401d (that is, AB = 21-16 = 5) to register 401c. Store in That is, 5 is stored in the register 401c.
    [53] When this process proceeds to 16 pixels, the final output of the counter 403 is 8, which is an APL value.
    [54] As described above, according to the APL calculation device in the PDP according to the present invention, the serial device uses a calculation of the APL which limits the power consumption or uses it as a reference signal for white balance adjustment in the display device expressing the gray scale according to the number of emission. By using a ding scheme, the number of gates can be saved considerably, which reduces hardware costs. That is, the number of gates can be reduced by only one register and one adder for accumulation, and by not using a divider that requires a lot of gates.
    [55] Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.
    [56] Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.
    权利要求:
    Claims (4)
    [1" claim-type="Currently amended] While the horizontal and vertical synchronization signals are both active, the input image data and the feedback data are added, and then the number of pixels per frame is reduced by the addition result or the addition result depending on whether the addition result is larger or smaller than the number of pixels per frame. An accumulator for storing a value;
    A comparator for comparing the addition result of the accumulator and the number of pixels per frame and outputting the result to the accumulator; And
    It is enabled while both horizontal and vertical sync signals are active, and is incremented only when it is determined by the comparator that the addition result of the accumulator is larger than the number of pixels per frame, and includes a counter for outputting an average luminance level value of the image. Apparatus for calculating the average brightness level of an image, characterized in that
    [2" claim-type="Currently amended] The method of claim 1,
    And an operation unit for performing an AND operation on the horizontal and vertical synchronization signals to output the enable signals to the registers and the counters of the accumulation unit.
    [3" claim-type="Currently amended] The method of claim 1, wherein the accumulation portion
    An adder for adding input image data and data fed back;
    A register which is enabled by an output of the operation unit and stores an addition result of the adder;
    A subtractor for subtracting the number of pixels per frame from the value output from the register;
    And a selector which selects an output of the subtractor when the output value of the adder is greater than the number of pixels per frame, and selects an output of the register and feeds it back to the adder when it is determined that the output value of the adder is larger than the number of pixels per frame. An average luminance level calculating device of an image.
    [4" claim-type="Currently amended] The method of claim 1, wherein the accumulation portion
    An adder for adding input image data and data fed back;
    If the comparator determines that the output value of the adder is larger than the number of pixels per frame, the selector selects a value obtained by subtracting the number of pixels per frame from the output of the adder, and selects and outputs the output of the adder if it is determined not to be large. Wow,
    A register which is enabled by the output of the calculator and stores a value output through the selector and feeds the stored value back to the adder;
    And a subtractor outputting the selector by subtracting the number of pixels per frame from the output value of the adder.
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    同族专利:
    公开号 | 公开日
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2002-04-04|Application filed by 엘지전자 주식회사
    2002-04-04|Priority to KR1020020018675A
    2003-10-11|Publication of KR20030080161A
    优先权:
    申请号 | 申请日 | 专利标题
    KR1020020018675A|KR20030080161A|2002-04-04|2002-04-04|Apparatus for calculating APL|
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